1. Field of the Invention
The present invention relates generally to methods for forming patterned conductor layers within integrated circuits. More particularly, the present invention relates to methods for forming residue free patterned conductor layers upon high step height integrated circuit substrates.
2. Description of the Related Art
As integrated circuit technology progresses towards increasingly higher levels of integration, conductor line-widths and conductor spacings within advanced integrated circuits have become increasingly smaller while the aspect ratios of those conductor lines have increased. In addition to characteristics which relate directly to the size and spacing of conductors within advanced integrated circuits, it is also common that conductors within advanced integrated circuits are formed upon substrate layers which have significant topographic variations such as substantial step height differentials. The sum of these factors often impedes production of fully functional and reliable patterned conductor layers within advanced integrated circuits.
One of the more common defects which occurs when photolithographically forming patterned conductor layers upon high step height integrated circuit substrates is the simultaneous formation of undesirable conductor layer residues at lower step levels within those integrated circuits. The undesirable conductor layer residues are typically formed at the lower step levels of the integrated circuit through incomplete etching of the blanket conductor layers from which are formed the patterned conductor layers. The presence of conductor layer residues at lower step levels within high step height integrated circuits may lead to electrical shorts and bridging within advanced integrated circuits.
Although it is possible to remove conductor layer residues from lower step levels through a more vigorous etching of the blanket conductor layer from which is simultaneously formed the patterned conductor layer and the conductor layer residues, such additional etching will typically substantially erode or otherwise damage the edges of the patterned conductor layer exposed beneath a photoresist etch mask while simultaneously removing the conductor layer residues. Thus, the present invention is directed towards the goal of removing undesired conductor layer residues from lower step levels within high step height integrated circuits while simultaneously maintaining the integrity of the patterned conductor layers which are formed simultaneously with the conductor layer residues.
Methods through which patterned features within integrated circuits may be protected from deterioration due to exposure to integrated circuit processing operations are known in the art. For example, Beitman, in U.S. Pat. No. 4,795,718 discloses a method for manufacturing an Insulated Gate Field Effect Transistor (IGFET) having self-aligned source/drain contact regions. The method employs forming a low melting point dielectric layer over the gate electrode of the IGFET device and heating the dielectric until it covers and encapsulates the gate electrode of the IGFET. The self-aligned source/drain contacts may then be formed without shorting to the gate electrode.
Although not directed towards the goal of encapsulating delicate integrated circuit features, Mitsuaki et al., in U.S. Pat. No. 4,981,809 describe a related method for forming fine mask patterns for use in producing advanced transistors. The method employs a patterned photoresist layer formed and subsequently annealed upon a semiconductor substrate. The annealing process reflows the patterned photoresist layer and forms smaller openings within the photoresist pattern. The smaller openings yield a fine mask pattern which is useful in forming advanced transistors.
Finally, Sung, in U.S. Pat. No. 5,371,025 describes a method for making Thin Film Transistors (TFTs) for use within Liquid Crystal Displays (LCDs). The method employs a patterned photoresist layer formed upon a gate electrode, which patterned photoresist layer is subsequently thermally re-flowed to form a mask which prevents channel overlap between the gate electrode and the source/drain electrodes of the Thin Film Transistor (TFT). Thin Film Transistors (TFTs) which have limited channel overlap exhibit a higher signal to noise ratio. Thus, they produce higher quality Liquid Crystal Displays (LCDs).
Desirable in the art is a method analogous to the above disclosed methods whereby thermal reflow properties of integrated circuit fabrication materials may be employed to assist in removing from high step height integrated circuits upon which have been formed patterned conductor layers conductor residue layers which are simultaneously formed upon lower step levels of those integrated circuits.